1. Field of the Invention
The invention relates generally to design rule test apparatuses, and more particularly, to a design rule test apparatus for testing if a mask pattern satisfies a design rule. The invention has particular applicability to computer aided design apparatuses for semiconductor integrated circuits.
2. Description of the Background Art
A large number of masks are used in a manufacturing process of a large-scale integrated circuit (hereinafter referred to as LSI). Pattern design of mask is generally conducted in accordance with a predetermined design rule. A design rule is generally determined taking account of processing accuracy in a manufacturing process, electrical characteristics and reliability, and a multiplicity of rules are prepared. A layout is designed to design a mask pattern. In designing a layout, a configuration of a circuit device and each location and orientation within the chip region, interconnection path, and mask patterns used in a manufacturing process are determined.
Generally, a design rule check is made in order to determine if the layout of the designed LSI satisfies a predetermined design rule. Examples of known items to be checked with respect to a design rule are a check of spacing, width, and overlaps of interconnection, and device parameters. In general, a design rule check is conducted by way of computers as designing of LSIs is performed utilizing a computer aided design apparatus (hereinafter referred to as CAD). While a large number of items are prepared as design rule check items, a design rule in a portion where an interconnection region and a contact hole region overlap, is particularly described in the following description.
FIG. 7 is a block diagram of a design rule check apparatus in a CAD system as a background of the present invention. Referring to FIG. 7, this CAD system includes a memory 300, an operation processing portion 400, a CRT 51, a keyboard 52, a mouse 53 and a plotter 54. The memory 300 includes a data file 31 for storing data of mask pattern configured in accordance with a layout design, and a design rule file 32 for storing data defining a variety of design rules. The operation processing portion 400 includes a design error recognition portion for determining if the designed mask pattern held in the mask pattern data file 31 satisfies the design rule in the design rule file, and then recognizing a design error, and an interface portion 43 for connecting input/output devices 51 to 54 to the design error recognition portion 41.
FIG. 8 is a plan view of a layout in the vicinity of a contact hole of a LSI. Referring to FIG. 8, the LSI includes a diffusion layer 7 formed in a semiconductor substrate, a first interconnection layer 4 connected to the diffusion layer 7 by way of the contact hole, and two second interconnection layers 1 and 2 formed on the first interconnection layer 4 over an insulating film. The second interconnection layers 1 and 2 are provided on a contact hole 10 having a width of W.
FIG. 9 is a sectional view of the LSI shown in FIG. 8 seen in the direction of an arrow 9. Referring to FIG. 9, a diffusion layer 7 is formed in a semiconductor substrate 6. A first interconnection layer 4 is connected to the diffusion layer 7 by way of a contact hole 10. An insulating film 3 is formed on the first interconnection layer 4. Second interconnection layers 1 and 2 are formed in the contact hole 10, and on the insulating film 3.
FIG. 10 is a sectional view of the LSI shown in FIG. 8 seen in the direction of an arrow 10. Referring to FIG. 10, a first interconnection layer 4 is connected to a diffusion layer 7. An insulating film 3 is formed over the first interconnection layer 4.
FIG. 11 is a sectional view showing interconnection material left between the second interconnection layers 1 and 2 shown in FIG. 8. Referring to FIG. 11, interconnection material 8 is left between the second interconnection layers 1 and 2, thereby short-circuiting the two interconnection layers 1 and 2. In general, when second interconnection layers 1 and 2 are formed, interconnection material is first formed on the insulating film 3 by way of evaporation. Then the interconnection material formed is patterned to have a predetermined configuration using a lithography and an etching methods. As a result, a predetermined portion of interconnection material is left, forming second interconnection layers 1 and 2. As shown in FIG. 11, however, a case occurs in which the interconnection material between the interconnection layers 1 and 2 cannot be removed completely by way of the etching method.
In order to prevent short-circuit between the interconnection layers 1 and 2 due to the interconnection material 8 left, it is necessary to set the width W of the contact hole 10 shown in 8 to over a predetermined value. The orientation of the width W is the same as that of the two interconnection layers 1 and 2. When the width W is set to over a predetermined value, short-circuit, which is due to the interconnection material 8 left between the interconnection layers 1 and 2 as shown in FIG. 11, is prevented. Accordingly, it is noted that a design rule check should be made in order to determine if the width W of the contact hole exceeds a predetermined value.
In a design rule check apparatus, for the abovementioned reason, there is a test for the width of the contact hole, in which a pseudo-error occurs as in the followings.
FIG. 12 is a plan view showing a relationship between the contact hole region and the interconnection region in layout. In the drawing, occurrence of a true design error and three pseudo-errors is shown. Referring to FIG. 12, four contact hole regions 14 to 17 are formed, with three interconnection layer regions 11 to 13 formed thereon. The width W0 shown in the drawing shows an allowable minimum value of a width of a contact hole which is predefined as a design rule. That is, when two or more interconnection layers are formed on the contact hole, it is required that the width of the contact hole should have at least a minimum value of W0. Therefore, the width W13 of the contact hole region 14 needs to be at or over the minimum value W0 as the interconnection layers 11 and 12 are formed on the contact hole region 14. The contact hole region 14, however, is displayed as a design error because W13&lt;W0.
The contact holes 15, 16 and 17 are represented as a design error inspite of the fact that none of these is required to be represented as a design error. Before describing the occurrence of a pseudo-error, a description is made as to recognition process in a conventional design error recognition portion 41 in the followings.
FIG. 13 is a flow diagram of the design error recognition portion 41 shown in FIG. 7. Referring to FIG. 13, in the step 61, a logical product operation (AND) is performed with regard to figures in a contact hole region and an interconnection layer region. Areas that are common to both contact hole region and interconnection layer region are detected, and the number of overlapping portions is detected. Then, it is determined if the number of overlapping portions NP is 2 or more (NP.gtoreq.2) in the step 62. If the number of overlapping portions NP is 1, there is no need to effect the following process with respect to the contact hole region.
If the number of overlapping portions NP is 2 or more, all the widths Wi (i=1, 2, . . . ) of the contact holes are detected in the step 63. All the widths Wi detected are compared with the minimum value W0 in the step 64. If at least one width Wi is below the acceptable minimum value W0, the contact hole region is recognized, and represented as a design error in the step 65. If all the widths Wi are at or above the minimum value W0, it is determined that the contact hole regions satisfy the design rule. In the step 66, it is determined if all the contact hole regions are tested, and the remaining contact hole regions are also subject to the same process as the above mentioned.
As the processing in the design error recognition portion 41 is effected as described above, a case occurs in which it is represented as a design error inspite of the fact that it is not essentially required to be treated as a pseudo-error, i.e., a design error shown in FIG. 12. The contact hole region 15 shown in FIG. 12 overlaps with the interconnection layer region 11 at two portions (NP =2), so that the process of the step 63 is effected. In the step 63, the widths W1 to W4 of this contact hole region 15 are compared with the minimum value W0. As the widths W3 and W4 are below the minimum value W0, this contact hole region 15 is recognized, and represented as a design error. In effect, this contact hole region 15, however, overlaps with a single interconnection layer region 11 at two portions, so that no problem of short-circuit as shown in FIG. 11 occurs. That means there is no need to treat this contact hole region 15 as a design error. Accordingly, it is noted that a pseudo-error occurs.
In the case of the contact hole region 16, this contact hole region 16 overlaps with the interconnection layer regions 11 and 12 at two portions, so that the process of the step 63 is effected. The widths W5 and W6 are above the minimum value W0. It is, however, detected that the width W7 is below the minimum value W0. As a result, this contact hole region 16 is recognized, and displayed as a design error in the step 65. It is apparent that there is also no problem of short-circuit as shown in FIG. 11 in this contact hole region 16. Accordingly, it is also noted that there is no need to treat this contact hole region 16 as a design error in this case.
In the case of the contact hole region 17, the contact hole region 17 overlaps with the interconnection layer regions 12 and 13 at two portions. It is determined that the widths W11 and W12 are below the minimum value W0 in the step 64, so that this contact hole region 17 is recognized, and represented as a design error in the step 65. In this case, however, it is pointed out that there is no problem due to short-circuit between the interconnection layers as in the above-mentioned two cases.
In the CAD system shown in FIG. 7, a large number of contact hole regions are displayed on the CRT 51, which are recognized as a design error by the comparison in the step 64 shown in FIG. 13. In the large number of contact hole regions recognized as a design error, exist together one representing the occurrence of a true design error and the other representing a pseudo-error as described above. Therefore, the operator has to determine if it is true or false with respect to an individual error displayed, referring to the layout displayed on the screen of the CRT 51. A multiplicity of contact hole regions and interconnections are provided in one LSI, so that the number of contact holes recognized as a design error is significant. As a result, it took a long time for an operator to determine it is true or false, reducing the efficiency of designing operation.